NXP Flash MCU to Atmel Flash MCU Cross Reference. 07/01/ 86KB. NXP Flash MCU to Atmel Flash MCU Devices, Non-Direct Replacements. 07/01/ The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and. 89C55 datasheet, 89C55 circuit, 89C55 data sheet: ATMEL – 8-Bit Microcontroller with 20K Bytes Flash,alldatasheet, datasheet, Datasheet search site for.
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89C55 (ATMEL) – 8-bit Microcontroller With 20k Bytes Flash | eet
Three-Level Program Memory Lock. Tamel device is manu- factured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C55 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
The AT89C55 provides the following standard features: In addition, the AT89C55 is designed with static logic amtel operation down to zero frequency and sup- ports two software selectable power saving modes.
The Power Down Mode saves the RAM con- tents but freezes the oscillator, disabling all other chip func- tions until the next hardware reset. The low-voltage option saves power and operates with a 2. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. In this mode, P0 has internal pul- lups.
Port 0 also receives the code bytes during Flash program- ming and outputs the code bytes during program verifica- tion. External pullups are required during program verifica- tion.
When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current I.
Port 1 also receives the low-order address bytes during Flash programming and verification. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current I. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use bit addresses MOVX DPTR.
89C55 Datasheet(PDF) – ATMEL Corporation
In this application, Port 2 uses strong internal pul- lups when emitting 1s. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current I.
Port 3 also serves the functions of various special features of the AT89C55, as shown in the following table.
Port 3 also receives the highest-order address bit and some control signals for Flash programming and verifica- tion. A high on this pin for two machine cycles while the oscillator is running resets the device.
RXD serial input port. TXD serial output port. INT0 external interrupt 0. INT1 external interrupt 1. T0 timer 0 external input.
T1 timer 1 external input. WR external data memory write strobe. RD external data memory read strobe. Note, however, that one ALE pulse is skipped during each access to external data mem- ory. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has amtel effect if the microcontroller is in external execution mode.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to V. This pin also receives the volt programming enable volt- age V. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect.
At89c55-24jc Atmel IC Microcontroller 8-bit 44 Pin PLCC MCU 89c55-24jc
User software should not write 1s to these unlisted qtmel tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers The individual interrupt enable bits are in the IE register.
Two atmeo can be set for each of the six interrupt sources in the IP register. The upper bytes occupy a parallel address space to the Special Function Registers.
Instructions that use direct addressing access SFR space. Instructions that use indirect addressing access the upper bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 whose address is 0A0H.
Note that stack operations are examples of indirect addressing, so the upper bytes 98c55 data RAM are avail- able as stack space. Search field Part name Part description.